The present invention relates to a semiconductor substrate of SiC or the like, a semiconductor device and a method for fabricating a semiconductor device, and more particularly, it relates to a technique to flatten an interface or a top face of a semiconductor layer.
In order to improve the operation speed and the performance of a semiconductor device, semiconductor materials other than silicon (Si) have been studied and developed all over the world.
One of new semiconductor materials is silicon carbide (SiC). Since SiC has a larger band gap than Si, it is expected to be applied to a power device, a high-frequency device and a high-temperature operating device of the next generation. Also, there are a large number of polytypes of SiC such as 3C—SiC (β-SiC) of the cubic system, 6H—SiC and 4H—SiC of the hexagonal system, and 15R—SiC of the rhombohedral system. Among these polytypes, 6H—SiC and 4H—SiC are generally used for fabricating a practical SiC-based semiconductor device, and a substrate having the (0001) plane vertical to the crystal c-axis of this polytype is widely used.
A SiC thin film is grown on a SiC bulk substrate generally by a step-controlled epitaxial growth technique. In this epitaxial growth technique, the step density on a substrate top face is increased by intentionally inclining the (0001) plane of the SiC bulk substrate at a small angle (of several degrees), so that a SiC thin film can be grown through step flow by the growth in a lateral direction of the step. When this technique is applied to SiC having a large number of polytypes, a thin film of the same polytype as that of a substrate can be advantageously grown because information of the cycle of atomic arrangement can be obtained from the step. Therefore, in the current technique, the (0001) plane serving as a reference plane is generally given an off angle of 8 degrees in 4H—SiC and of 3.5 degrees in 6H—SiC in the [11-20] direction.
Now, a SiC substrate used in a SiC-based semiconductor device and a method for fabricating the SiC substrate will be described.
FIG. 18 is a diagram for schematically showing a general vertical thin film growth system for growing a SiC layer.
As shown in FIG. 18, the vertical thin film growth system for SiC includes a reactor 1120, a susceptor 1122 of carbon, a support axis 1123 for supporting the susceptor, a coil 1124 coiled around the reactor 1120 for heating, a gas supply system 1128 for supplying, to the reactor 1120, a material gas 1125, a carrier gas 1126 and a dopant gas 1127, a gas exhaust system 1129 for evacuating the reactor 1120, an exhaust pipe 1130 for connecting the reactor 1120 and the gas exhaust system 1129, and a valve 1131 provided on the exhaust pipe 1130. The pressure within the reactor 1120 is controlled by using the valve 1131.
In epitaxially growing a SiC thin film, a substrate 1121 is placed on the susceptor 1122, and the material gas 1125, the carrier gas 1126 and the dopant gas 1127 are supplied from the gas supply system 1128 to the reactor 1120. At this point, the susceptor 1122 is heated through high frequency induction heating using the coil 1124, and hence, the substrate temperature is increased to an epitaxial growth temperature. Also, cooling water is circulated in a peripheral portion 1132 of the system.
FIGS. 19A and 19B are cross-sectional views for showing a method for fabricating a conventional SiC substrate having a SiC multilayered structure using the vertical thin film growth system. FIG. 20 is a diagram for showing change with time of various conditions for the growth of a conventional SiC thin film. Now, a method for fabricating a conventional SiC substrate will be described with reference to these drawings.
First, in a procedure shown in FIG. 19A, a SiC bulk substrate 1101 is placed on the susceptor 1122 of the vertical thin film growth system. Then, a hydrogen gas is introduced as the carrier gas 1126 from above the reactor 1120, and the pressure within the reactor 1120 is adjusted to an atmospheric pressure or less by using the valve 1131. Under this condition, the SiC bulk substrate 1101 is annealed, so as to increase the substrate temperature to the epitaxial growth temperature, that is, 1500° C. or more.
Next, as shown in FIG. 20, without changing the flow rate of the hydrogen gas, a gas including carbon (such as a propane gas) and a gas including silicon (such as a silane gas) are introduced as the material gas 1125 at certain flow rates. Thus, SiC crystal is epitaxially grown on the top face of the SiC bulk substrate 1101. At this point, the pressure within the reactor 1120 is set to 90 kPa. In the case where an n-type doped layer is to be grown, for example, nitrogen is introduced as the dopant gas 1127, and in the case where a p-type doped layer is to be grown, for example, trimethyl aluminum is introduced from the gas supply system 1128 to the reactor 1120.
Then, in a procedure shown in FIG. 19B, with the flow rates of the hydrogen gas (i.e., the carrier gas 1126) and the silane gas and the propane gas (i.e., the material gas 1125) fixed as shown in FIG. 20, desired SiC thin films, such as an undoped layer including no dopant, a p-type doped layer and an n-type doped layer, are deposited on the substrate. At this point, the SiC thin films are deposited so that two layers adjacent to each other with an interface sandwiched therebetween can respectively include a dopant in different concentrations or respectively include dopants of different conductivity types. Hereinafter, a portion in which a plurality of SiC thin films are thus deposited is designated as a SiC multilayer part 1103, and a portion of the SiC bulk substrate in contact with the SiC multilayer part 1103 is designated as a SiC bulk substrate top face 1102.
Subsequently, the supply of the propane gas and the silane gas is stopped and the annealing of the substrate is stopped, so as to end the growth of the SiC thin films. Thereafter, the resultant substrate is cooled in a hydrogen gas atmosphere.
The conventional SiC substrate fabricated in the aforementioned manner includes the SiC bulk substrate 1101 and the SiC multilayer part 1103 epitaxially grown on the SiC bulk substrate 1101.
In the conventional SiC substrate, the number and the combination of SiC thin films included in the SiC multilayer part 1103 may be changed depending upon the type of device in which the substrate is to be used. For example, when an undoped layer and an n-type doped layer are successively grown on the SiC bulk substrate 1101 with a gate electrode, a source electrode and a drain electrode provided on the n-type doped layer, a MESFET (Metal Semiconductor Field Effect Transistor) can be fabricated. Alternatively, when an n-type SiC layer, a p-type SiC layer and an n-type SiC layer are deposited in this order in the upward direction in the SiC multilayer part 1103, a pn diode can be fabricated.
Alternatively, a semiconductor device without the SiC multilayer part 1103 can be fabricated by using the same thin film growth system.
In the conventional method for fabricating a SiC substrate, however, since a SiC film is grown on a substrate inclined at an off angle as described above, sawtooth-shaped irregularities, which is designated as macro steps, are disadvantageously formed on the top faces of the SiC bulk substrate and the SiC thin film.
The macro steps 1104 shown in FIGS. 19A and 19B are caused by combining several or several tens steps of atomic layers larger than a monolayer, and in general, a step height (indicated as α in FIG. 19A) is 50 nm or more and a terrace width (indicated as β in FIG. 19A) is 500 nm or more.
Therefore, when the conventional SiC substrate having the macro steps 1104 is used for a semiconductor device, good electric characteristics innate in SiC cannot efficiently lead to the performance of the semiconductor device. For example, when it is used for a Schottky diode, an electric field is collected at the tip of the macro step in a Schottky electrode provided on a SiC thin film, so as to disadvantageously lower the breakdown voltage. Alternatively, when it is used for a MESFET in which the surface layer of a SiC thin film is used as a channel, carriers are disturbed by the macro steps, and hence, the carrier mobility is lowered so as to disadvantageously lower the mutual conductance. Further alternatively, when it is used for a MESFET in which a gate insulating film is formed on the top face of a SiC thin film, the oxide film has different thicknesses between a step wall and a terrace of the macro step, and hence, an inverted layer formed under application of a gate voltage has an uneven thickness, so as to disadvantageously lower the channel mobility.
In this manner, even when a conventional SiC substrate is used for fabricating a semiconductor device, electric characteristics that can be expected based on good physical property values innate in SiC cannot be attained by the conventional method.
The aforementioned disadvantages particularly clearly appear when an epitaxially grown SiC thin film has a small thickness. This is because, when the size of the macro step is large as compared with the thickness of the SiC thin film, the macro step relatively largely affects the device characteristic. In addition, when the grown SiC thin film has a multilayered structure as shown in FIG. 19B, the influence on the device using the SiC substrate is further larger.
An example of the multilayered structure of a SiC thin film is a δ-doped multilayered structure. A δ-doped layer is a layer that has a thickness of approximately 10 nm, includes a dopant in a high concentration and has an abrupt concentration profile. In the δ-doped multilayered structure, a combination of a δ-doped layer and an undoped layer including a dopant in a concentration lower by one or more figures than the δ-doped layer is repeatedly formed. When the δ-doped multilayered structure is utilized for a semiconductor device, the fabricated semiconductor device can attain a high breakdown voltage property capable of operating at a high speed. In other words, in employing the δ-doped multilayered structure, when the semiconductor device is in an off state, the entire active region is depleted and hence the breakdown voltage can be increased, and when the semiconductor device is in an on state, carriers leached from the δ-doped layer can move through the undoped layer with a small resistance, and hence, the carrier mobility can be large. In a device using this structure, however, the thickness of a layer serving as a channel region or the like is controlled at the level of 10 nm, and therefore, the irregularities of the macro steps largely harmfully affect the device, and hence, the mobility is unavoidably lowered.
As described so far, in the case where a conventional SiC substrate is used, the macro steps are formed not only on the top face of a SiC bulk substrate but also on an interface between SiC thin films, and the irregularities are caused also in the δ-doped multilayered structure. Therefore, it is difficult to obtain electric characteristics expected based on the good physical property values innate in SiC. Accordingly, there are increasing demands for a SiC substrate and a semiconductor device in which not only the top face but also the interface between SiC thin films is flat.
Although there was a report in consideration of the flatness of the top face alone of a SiC film, as in a method described in the transactions of Japanese Electro-technical Committee, 2001, vol. 121, No. 2, p. 149, there has been no report on a technique in consideration of the flatness on an interface between deposited SiC layers. Also, even when the flatness on the top face is considered, it has been difficult to fabricate a device sufficiently and efficiently utilizing the good characteristics of a material.
Also, the performance lowering of a device derived from the macro steps occurs not only in a SiC substrate but also in a SiGe substrate, a GaN (gallium nitride) substrate and a GaAs substrate inclined by an off angle. Therefore, a method for suppressing macro steps applicable to growth of a material other than SiC is desired.